1. Field of the Invention
This invention relates to an improved metal interconnect for an integrated circuit structure. More particularly, this invention relates to a metal interconnect stack for an integrated circuit structure wherein a protective layer is added to the metal stack to inhibit reaction with an underlying tungsten-filled via or contact opening.
2. Description of the Related Art
Integrated circuit structures include metal interconnects to provide electrical connections between active and passive devices which form part of the integrated circuit structure. These generally horizontal metal interconnects, in turn, connect to generally vertical metal-filled vias or contact openings to provide both horizontal and vertical electrical access or connections throughout the integrated circuit structure.
As shown in prior art FIGS. 1 and 2, aluminum and copper, and their alloys, including aluminum/copper alloys, are at present, the materials of choice for the formation of a main metal interconnect layer 6 of a metal interconnect stack 1. However, due to the interaction of aluminum and/or copper with other materials, such as A silicon substrate, a lower barrier layer 4 and an upper barrier layer 8 are usually provided, respectively, below and above main aluminum/copper metal interconnect layer 6. Titanium nitride (TiN) is, at present, a popular material for use in formation of such barrier layers 4 and 8.
It has been found that to maximize electron migration through main aluminum/copper metal interconnect layer 6, main layer 6 should be composed of crystallographic grains with &lt;111&gt; orientation. To achieve such crystallographic orientation, it is very important that underlying TiN barrier layer 4 also has this &lt;111&gt; crystallographic orientation, since TiN barrier layer 4, below main aluminum/copper metal interconnect layer 6, acts as a seed layer during the CVD or PVD formation or deposition of main aluminum/copper metal layer 6. However, to achieve a &lt;111&gt; orientation of underlying TiN barrier layer 4, it has been found necessary to first provide a titanium metal layer 2 beneath TiN barrier layer 4 which when its surface had been cleaned to remove contaminates, in turn, acts as a seed layer for the formation of TiN barrier layer 4 with a &lt;111&gt; orientation.
Thus, conventional prior art metal interconnect stack 1, as shown in FIGS. 1 and 2, comprises a titanium metal seed layer 2 having a cleaned surface thereon, lower TiN barrier layer 4 thereon having a &lt;111&gt; crystallographic orientation, a &lt;111&gt; aluminum/copper main metal interconnect layer 6 over TiN barrier layer 4, and upper TiN barrier layer 8 formed over aluminum/copper main metal layer 6.
The metal-filled vias or contact openings beneath the metal interconnect stack 1 provide vertical electrical connection either as metal-filled vias to an underlying metal interconnect stack or as metal-filled contact openings, for example, to underlying active or passive devices of the integrated circuit structure.
As shown in FIGS. 1 and 2, an insulation layer 14, such as silicon oxide (SiO.sub.2) 14 is formed over an existing integrated circuit structure 12 (which may comprise a semiconductor substrate with active devices constructed therein, or may further comprise such structure as well as a lower insulation layer and a first metal interconnect stack already formed beneath insulation layer 14). A via or interconnect opening 16 is formed in insulation layer 14 down to underlying integrated circuit structure 12, and via 16 is filled with a conductive metal plug 20.
Currently tungsten is the metal of choice used to form metal plug 20 to fill such vias or contact openings 16, which in turn, make electrical contact with titanium layer 2 comprising the lowest layer of metal interconnect stack 1.
However, as shown in prior art FIGS. 1 and 2, sometimes metal interconnect stack 1 and tungsten plug 20 in via or contact opening 16 are misaligned with respect to one another, resulting in exposure of a portion 22 of the upper surface of tungsten plug 20 (which surface should be completely covered by metal interconnect stack 1).
Such misalignment results in an exposure of portion 22 of the upper surface of the tungsten plug 20 which can cause a corrosion problem which may, in turn, lead to failure of the integrated circuit structure. This is because the exposed titanium/tungsten interface, upon being contacted by either wet etchants used to pattern the metal interconnect stack or cleaning solutions used to clean the structure to remove etch residues after the etch step, can form a galvanic cell, with titanium layer 2 and tungsten plug 20 forming the electrodes and the etchant/cleaning solution acting as the electrolyte. This, in turn, can result in attack and erosion of tungsten plug 20, as well as oxidation of titanium layer 2.
Since some horizontal misalignment between metal interconnect stack 1 and tungsten plug 20 may occur, however infrequently, it would be of great benefit if the metal interconnect stack could be modified to inhibit such galvanic interaction between the tungsten plug in the via or contact opening and the titanium layer in the metal interconnect stack.